1. Field of the Invention
This invention relates generally to a cascadable, synchronous divide-by-two counter and, more particularly, to a cascadable, synchronous divide-by-two counter that employs bipolar transistors in a low power and low cost mixed-signal device.
2. Discussion of the Related Art
Cellular telephone base stations employ several RF transmitter and receiver circuits for processing cellular telephone signals. Cellular telephone signals transmitted from a mobile unit are received by a receiver circuit in the base station, and demodulated and processed therein to decode the signal. The decoded signal is then transferred to a land line or to a transmitter circuit in the base station. The transmitter circuit modulates the information to be transmitted onto a carrier wave for transmission. The transmit and receive signals are typically at a frequency in the range of 800-2000 MHz, where the transmit signal and the receive signals are at different frequencies within a given frequency band with a fixed offset between the signals.
Each receiver circuit typically employs two channels, a primary channel and a diversity channel, each having a separate antenna, so that the receiver circuit can select which of the two receive signals is the strongest for subsequent processing. Some receiver circuits combine the primary channel and diversity channel signals for increased performance. This allows the receiver to be more reliable by lessening the chance that cellular calls are dropped. However, receivers of this type have been limited in their effectiveness for reducing circuit components, while maintaining signal fidelity at high frequencies.
A key function in a cellular telephone system of the type discussed above is the ability to test that the transmitter circuit is operating properly and producing a signal compatible with system requirements. This is commonly done by xe2x80x9cloopingxe2x80x9d a transmit signal back to the receiver circuit in the system to verify that the transmitter and the receiver are operating properly. Because the transmit signal and the receive signal are at different frequencies, a special RF loop-back self-test circuit is required to convert the transmit signal to the receive signal frequency so that the loop-back test can be performed without disturbing the on-going transceiver operation.
Known RF loop-back self-test circuits typically require a separate phase lock loop (PLL) circuit to generate a local oscillator (LO) signal that provides the offset between the transmit signal frequency and the receive signal frequency. The PLL circuit includes various amplifiers and other system components that are compatible with the system requirements. Further, the known self-test circuits require a mixer circuit to convert the signal to an intermediate frequency (IF), or IF to RF. The known loop-back self-test circuits required many integrated circuits and discrete parts, i.e., separate mixers, buffer amplifiers, switches, voltage controlled oscillators, PLLs, to generate the LO signal and switching at significant cost and size. Further, the known self-test circuit designs are typically point designs that do not have the flexibility to change divide ratios and modes of operation to tune the LO frequency by software control for the different frequency offsets between the transmit and receive signals in the many different base stations.
In accordance with the teachings of the present invention, a cascadable, synchronous divide-by-two binary counter circuit is disclosed that has particular application for use in a divider circuit in a phase lock loop, for example, a phase lock loop in a loop-back self-test circuit. The divider circuit would include the number of binary counter circuits necessary to provide the desired count based on 2n.
The counter circuit employs a D flip-flop that receives a D input and provides a Q output. A first AND gate is responsive to a logic P input and a logic Q input, where the Q input is the output from a preceding counter circuit and the P input is the state of all of the preceding counter circuits. The P input for a particular counter circuit is a logic high only if the P outputs from all of the preceding counters are a logic high. The output of the first AND gate is applied to an exclusive-OR gate along with the Q output of the flip-flop. The output of the exclusive-OR gate is applied to one input of a second AND gate. The other input of the second AND gate is a reset signal, and the output of the second AND gate is the D input of the flip-flop. Each clock transition causes the flip-flop to transfer the D input to the Q output. Each separate counter circuit in the cascade is reset by the same reset signal, and a decoder is programmed to provide the reset signal when the desired count is reached.
Additional objects, advantages and features of the present invention will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings.